Intel doesn’t plan to bring 3D V-Cache-like tech to consumer CPUs for now — next-gen Clearwater Forest Xeon CPUs will feature “Local Cache” in the base tile akin to AMD’s 3D V-Cache

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Intel doesn’t plan to bring 3D V-Cache-like tech to consumer CPUs for now — next-gen Clearwater Forest Xeon CPUs will feature “Local Cache” in the base tile akin to AMD’s 3D V-Cache

Intel doesn’t plan to bring 3D V-Cache-like tech to consumer CPUs for now — next-gen Clearwater Forest Xeon CPUs will feature “Local Cache” in the base tile akin to AMD’s 3D V-Cache

Clearwater Forest is turning out to be an entirely different beast – incorporating not only the latest goods from Intel Foundry – like Foveros Direct 3D, RibbonFET, PowerVia, and EMIB 3.5D – but also 3D cache, which Intel terms as “Local Cache,” per an interview with Intel’s Florian Maislinger conducted by der8auer and Bens Hardware. Furthermore and sadly, Team Blue also says it has no plans to introduce AMD 3D V-cache-esque capabilities in its desktop CPUs.

Intel’s next-generation E-Core, only Xeon series codenamed “Clearwater Forest,” will leverage its flagship 18A node—on which Pat Gelsinger has staked the entire company’s future. Clearwater Forest is expected to use Atom Darkmont cores, succeeding the already-fast Skymont featured in Lunar Lake and Arrow Lake CPUs.

From an architectural and packaging standpoint, Clearwater Forest uses three “active” Base tiles – each hosting four CPU chiplets or tiles for 12 CPU tiles connected via Hybrid Bonding (Foveros 3D Direct). On the outskirts lie two I/O chiplets – connected to the CPU tiles through EMIB 3.5D. The entire package is expected to feature almost 300 billion transistors.

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(Image credit: Intel via SemiWiki)

Maislinger stated, “But for us, this (gaming) is not an extremely large mass market. You still have to see that we sell a lot of CPUs that are not necessarily used for gaming. We still have it (3D Stacked Cache) technologically. This means that next year there will be a CPU (Clearwater Forest) for the first time that has a cache tile, but not on desktop.”

The interview confirms something we’ve missed: how the cache is structured. A quick look at Intel’s white paper clarifies that the SRAM is packaged into the Base tile, which Intel calls “Local Cache.” Until now, even with a disaggregated design, Intel has employed “Compute Tiles” featuring all cores alongside their respective caches linked via the Ring Bus. Clearwater Forest shifts the cache to the Base tile beneath the CPU chiplets, which now only hosts the CPU cores – and the entire assembly acts as a “Compute Module.” However, this is unlike AMD’s X3D approach since the CPU chiplets are mutually dependent on the Base tile.

Afterward, Florian Maislinger asserted that Intel’s gaming market is relatively small, and designing an X3D competitor would be pointless if it could not be reused for servers. On a side note, AMD is also looking to introduce 3D V-Cache in Threadrippers. It shows that Intel (or rather Intel Foundry) does have the technology to combat AMD’s 3D V-Cache, Clearwater Forest, but it is not planning to make it mainstream anytime soon.

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